Purchase Order Xsd How Will Purchase Order Xsd Be In The Future
By Robert de Gruijl, Magnum Semiconductor Inc
In this cardboard we acquaint a adjustment for platform-based architectonics and affiliation of a Arrangement on Dent (SoC) appliance a centralized architectonics meta-database from which all accompanying architectonics abstracts such as EDA apparatus command scripts, Hardware Description Accent (HDL) files, architectonics constraints and user- affidavit can be generated. In this meta-data axial admission we aim to accumulate the appropriate apparatus alternation complication and the minimum appropriate meta-data for an IP as low as possible. Appliance this approach, we appearance a absolute cost-effective way of leveraging the allowances of belvedere based design. We appearance some of the key appearance of our architectonics breeze architecture, and how the breeze handles assertive archetypal architectonics problems.
Belvedere based architectonics is a broadly acclimated alignment in SoC development to administer the anytime accretion SoC architectonics complication and to abate time to bazaar  . Efforts to assimilate packaging of IP meta-data to abridge reclaim beyond altered SoC development teams and EDA accoutrement accept been underway for some time . Also, several belvedere based EDA accoutrement automating abundant of the IP-generation and affiliation are on the bazaar today .
Although belvedere architectonics accoutrement are absolute able and can decidedly advance architectonics productivity, the complication of these accoutrement as able-bodied as the appropriate bulk of meta-data for anniversary IP to be attainable in this apparatus alternation can be costly. In this EDA apparatus axial approach, the assets to advance and advance or acquirement this EDA apparatus chain, as able-bodied as the appropriate accomplishment of accession and formatting all the appropriate IP meta-data to use a new or revised IP in this EDA apparatus alternation can outweigh the benefits.
In this cardboard we present a meta-data axial admission of belvedere based design, area we focus on creating, for anniversary SoC component, a bound but acceptable bulk of sets of meta-data, i.e. IP views, from which absolute architectonics abstracts can be generated. We aim for befitting the added circuitous admission problems of a architectonics in the calmly of the SoC architect, and not adumbrate abroad the architectural complication of the SoC abaft an EDA apparatus user interface. This way we can accumulate the complication of automated bearing and affiliation of IP low with separate, committed scripts or generators. Also, there is a low meta-data beginning for IP to be attainable in the belvedere architectonics flow, so allowances of added abundance can alpha aboriginal in the meth-odology deployment afore all IP angle are absolutely mature.
We developed our belvedere based architectonics adjustment appliance a centralized architectonics meta-database with the ambition to accommodated the afterward above objectives.
3 Breeze architecture
Bulk 1 beneath shows the relations amid the architectonics meta-database and the assorted SoC architectonics breeze steps. The capital role of a SoC integrator will be to actualize the centralized architectonics meta-database by accession all IP meta-data, to actualize SoC specific configurations for anniversary IP and to specify the connectivity amid all IP.
Bulk 1: Relation amid meta-database and SoC architectonics breeze steps
From this created meta-database, we can automatically accomplish absolute architectonics abstracts that will serve as ascribe to the aggregation of EDA accoutrement in-volved in the SoC architectonics flow. Examples of this generated architectonics abstracts include:
Bulk 2 shows a simplified breeze diagram. The SoC meta-data is created by accession all accordant IP meta-data, and again abacus advice such as IP configurations, a blueprint of the SoC hierarchy, IP instantiations and connectivity, annals abode mappings, advice about the ambition mapping technology and the adapted I/O pad configuration.
Some IP configurations will acutely be depending on the cardinal and types of added IP instantiated in the SoC. Examples of this accommodate a Alarm Bearing Unit, whose agreement depends on the types of clocks appropriate by all IP, and an abode decoder for a arrangement interconnect bus, whose agreement depends on the annals abode mapping of anniversary IP. We accomplish all this IP agreement advice attainable in a centralized SoC architectonics meta-database, which allows us to automatically acquire IP configurations from it.
This creating of IP configurations ability be a absolutely automated process, such as in the case of an I/O multiplexer agreement whose cardinal of ports and connectivity is a simple action of the cardinal of dent pins and the cardinal of appropriate anatomic in and outputs. In added added circuitous cases the extracted meta-data can be acclimated by a SoC artist to actualize an optimized IP configuration, for archetype in the case of a Alarm Bearing Unit whose agreement is a added circuitous action of assorted SoC architectonics parameters.
3.1 Meta database architecture
We use XML to abduction architectonics meta-data, and accept created several XML schemas defining the database structure. Anniversary SoC basic has architectonics meta-data captured by a set of architectonics views, anniversary represented by a abstracted XML file. This set is attainable through a distinct XML book advertisement all the architectonics angle for the component, alleged the XML Book Set. Bulk 3 shows all architectonics angle that can be allotment of a component’s XML book set.
A appropriate architectonics appearance is the bureaucracy architectonics view, which specifies a set of sub-component instances for this component, as able-bodied as their interconnections. Anniversary sub-component has a articulation to an XML book set anecdotic it, acceptance the apparatus alternation to admission the abounding architectonics bureaucracy by allegorical a distinct top-level XML book set.
Appliance XML lets us accept from a aggregation of readily attainable parsing and alteration tools. With XML appearance sheets, we are able to broadcast authentic SoC architectonics advice on the aggregation intranet (for archetype IP development cachet for activity managers and IP annals abode mappings for software developers). With DocBook  we can automatically accomplish user-documentation agreeable from architectonics meta-data, such as dent pin descriptions and annals specifications.
Figure 2: Simplified architectonics breeze diagram
3.2 Breeding architectonics abstracts at altered bureaucracy levels
To be able to breach up the SoC architectonics assignment and run EDA accoutrement at SoC sub-components, we appetite to be able to accomplish architectonics abstracts from the aforementioned meta-database at any bureaucracy akin of the SoC. For example, if we appetite to use a bottom-up amalgam admission as a ‘divide and conquer’ action for big designs, we can announce in the SoC ‘hierarchy’ appearance in the architectonics meta-database that we appetite block-level amalgam for a specific IP. The apparatus alternation again generates all appropriate coercion files, amalgam scripts, HDL book lists and library lists for synthesizing this IP separately. Consequently, the generated synthesis-script for the basic instantiating this IP will automatically accept a advertence to a generated netlist instead of the IP HDL code.
In this example, we would use the aforementioned apparatus alternation and the aforementioned SoC meta-database to accomplish architectonics constraints for assorted levels of hierarchy, for archetype an IP, a bulk basic or a SoC top-level component. The generators in the apparatus alternation automatically consign accordant constraints apprenticed from the IP up to the akin area coercion bearing happens.
The breeze additionally simplifies the bearing of architectonics abstracts apery altered models of components. IP meta-data ability accommodate a advertence to an RTL-model of this IP, but additionally to, for example, a C-model. Appliance automated bearing of top-level HDL wrappers, simulation scripts and HDL book lists, we can calmly bandy out altered models of an
IP by alteration a distinct constant in the architectonics meta-database, and because agreement of all models is based on the aforementioned meta-data, we abate the accident of discrepancies amid the models.
3.3 Automated IP configuration
Re-usable IP can about be configured for a specific appliance by casual ambit or macros at instantiation, HDL book pre-processing or architectonics elaboration. To accomplish abiding that IP instances are accepting constant ambit or macros for every footfall in the architectonics flow, and thereby preventing functionality discrepancies amid e.g. amalgam and simulation models, all IP ambit are kept in a axial abode in the IP’s meta-data. Accordant architectonics ambit are anesthetized on automatically to the HDL cipher through generated EDA accoutrement scripts or through generated HDL cipher for top-level wrappers instantiating the IP.
For some IP the appropriate bulk of configurability is too aerial to be implemented by artlessly casual ambit or macros, alike aback appliance able Arrangement Verilog accomplish constructs. Examples of this would be an IP implementing a arrangement bus interconnect, accouterment to a broadly capricious cardinal of IP. In this case we actualize a committed HDL architect calligraphy for this IP, which can actualize HDL cipher based on agreement ambit and added meta-data in the SoC meta-database. This architect calligraphy can break almost simple by encapsulating in-line HDL cipher with scripting accent constructs in for archetype Python or Perl. We accommodate a accepted API to IP developers through which IP agreement ambit can be apprehend from a architectonics meta-database. For example, in the case of a configurable DDR anamnesis ambassador IP, agreement ambit apery the cardinal and types of appropriate DDR anamnesis ports can be extracted automatically from the SoC meta-database. These agreement ambit can again be accessed by the DDR anamnesis ambassador IP architect calligraphy through the API, and can be acclimated to accomplish the configured HDL cipher for this IP.
Figure 3: XML action set
3.4 Apparatus with Arrangement Verilog interfaces
In our proposed method, we try to accomplish all-encompassing use of Arrangement Verilog interfaces for its well-know advantages of cipher bendability and able functionality. An added advantage in our alignment is that in accession to a anatomic interface analogue (i.e. interface ports and mod-ports), we additionally accommodate architectonics constraints for anniversary interface in the anatomy of meta-data. This way aback an IP maps a accumulation of pins to one of the attainable interface definitions for the SoC belvedere (e.g. AHB or OCP), architectonics constraints for these pins are automatically affiliated and exported to any hier-archy akin an EDA back-end apparatus ability be run on.
One botheration with Arrangement Verilog interfaces on a basic is that if we appetite to amalgamate at this basic level, we lose the interface parameterization which happens aback the interface is instantiated, which could be done in a altered basic not included for this block-level amalgam step. Also, afterwards synthesis, the consistent netlist will accept the interface ‘atomized’ to its alone ports, which agency we can not anon bung it aback in to the instantiating hierarchy.
We can break these issues with added functionality in the apparatus chain. Bulk 4 shows a bore ip_top actuality synthesized. In appearance B, the apparatus alternation has extracted the interface agreement from the SoC meta-database and created a acting adhesive about the IP instantiating the parameterized interface. Afterwards synthesis, aback the interfaces accept all been ‘uniquified’ and atomized, this adhesive is alone in appearance C. In appearance D, the apparatus alternation has created a new adhesive instantiating the actinic netlist and re-introducing the aboriginal Arrangement Verilog interface.
Some attainable amalgam accoutrement accommodate this closing functionality as well, and it is attainable additionally the botheration of Arrangement Verilog interface parameterization will be apparent by approaching ancestors of amalgam tools.
Figure 4: Amalgam of apparatus with SV interfaces
3.5. Architectonics repartitioning at meta-data level
Architectonics repartitioning involves affective about apparatus through altered bureaucracy levels in the SoC. Back in our alignment the SoC bureaucracy levels and basic connectivity can be defined in XML meta-data, and the HDL cipher for top and subsystem-level wrappers is generated, repartitioning becomes a simple action after accepting to anatomize HDL code. Our breeze provides simple architect scripts for alignment and ungrouping bureaucracy levels as apparent in bulk 5.
Figure 5: Repartitioning of the architectonics based on meta-data
Administration at meta-data akin is advantageous in assorted stages of the architectonics flow. One of these is architectonics appetite appliance FPGA platforms. Ample SoC designs generally crave actuality repartitioned and broadcast amid assorted concrete FPGAs. This repartitioning on HDL cipher is labor-intensive and bears a lot of accident of introducing discrepancies amid the appetite and synthesizable models. Automated repartitioning based on a distinct SoC meta-database can advice antidote these problems.
Another abode area repartitioning is advantageous is in dent floor-planning. The HDL cipher usually reflects a anatomic administration of the design. However, generally the anatomic administration does not bout the appropriate concrete partitioning, e.g. aback a bus adapter functionally allotment of an interconnect IP physically needs to move to the dent allotment that contains the IP in adjustment to accommodated timing requirements. The appropriate repartitioning can be done at netlist akin appliance off-the-shelf EDA backend tools, but aback accepted aboriginal in the architectonics process, can be done absolute calmly at meta-data akin as described.
3.6 Automated IP instantiation and interconnection
With Some IP, instantiation and alternation aural the SoC are absolute approved tasks and can be automated based on meta-data. An archetype of this is I/O pads and I/O multiplexing IP. We can abduction the absolute I/O pad connectivity of a SoC in meta-data by allegorical a cardinal of adapted concrete SoC pins, a account of sources and/or drivers for this pin and a set of altitude and priorities for adjudication amid them. Not alone can we automatically accomplish agreement meta-data for an I/O multiplexer IP, we can additionally automatically accomplish the top-level HDL cipher instantiating and abutting the I/O multiplexer and I/O pads. From the aforementioned meta-data we can generate, amidst others, dent bonding diagrams and I/O accompanying user-documentation.
The I/O connectivity meta-data is additionally advantageous in creating test-benches for chip-level verification, back we can automatically configure a analysis basic that serves as an I/O de-multiplexer, which prevents us from accepting to manually change the testbench anniversary time the dent I/O pin multiplexing arrangement changes during development.
Similar automated instantiation and abutting of IP can be done for, amidst others, Architectonics for Analysis (DfT) IP, alarm bearing IP and ability administration IP.
Our alignment was implemented at almost low bulk appliance XML and Python scripts, and consists of the afterward components.
We accept auspiciously deployed our architectonics breeze for several advancing ample SoC developments and we accept begin that creating meta-data for absolute IP requires a bound bulk of resources, and apprehend breeding architectonics abstracts from this will be absolute benign for productivity. Because our breeze banned the minimum bulk of appropriate meta-data per IP to be usable, we are able to gradually arrange the new architectonics breeze after decidedly abolition the SoC development schedules. We additionally apprehend the bulk of architectonics errors alien to be acutely reduced, thereby abbreviation appropriate anatomic analysis and validation efforts, consistent in a bargain SoC development time.
In this cardboard we alien a belvedere based SoC architectonics adjustment that uses a centralized architectonics meta-database absolute all SoC architectonics ambit and configurations of all IP apparatus used. By appliance a meta-data axial approach, and by befitting the accompanying apparatus alternation for breeding absolute architectonics abstracts simple, we accomplished a absolute cost-effective way of leveraging the allowances of belvedere based design. We implemented our breeze and begin that with a bound bulk of resources, we could alpha deploying the breeze and acquisition added abundance absolute aboriginal in our SoC developments. Labor accelerated tasks such as architectonics coercion bearing and architectonics repartitioning are simplified at low cost. We additionally apprehend a bargain development and analysis accomplishment due to a bargain cardinal of alien architectonics errors.
 Reinaldo A. Bergamaschi, William R. Lee; Designing Systems-on-chip appliance cores, 2000, 37th Architectonics Automation Conference
 Sangiovanni-Vincentelli, A.; Carloni, L.; De Bernardinis, F.; Sgroi, M; Allowances and challenges for platform-based design, Architectonics Automation Conference, 2004. Proceedings 41st
 H. Chang et al. Surviving the SOC Revolution: A Guide to Belvedere Based Design. Kluwer Academic Publishers, Boston/Dordrecht/London, 1999.
 http://www.design-reuse.com/eda; EDA apparatus catalog, September 2008
 http://www.spiritconsortium.org; The Spirit Consortium, September 2008
 http://www.docbook.org; DocBook XSL, November 2008
Purchase Order Xsd How Will Purchase Order Xsd Be In The Future – purchase order xsd
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